The critical dimension (CD) of semiconductor devices becomes very small along the development of semiconductor technology, and integrating more semiconductor devices in a two dimensional (2D) package structure becomes much more difficult. A three dimensional package structure becomes an effective way to achieve a higher integration. The 3D package technology includes: die stacking and package stacking, both based on gold wire bonding, and TSV-based 3D package structure. The advantages of TSV-based 3D package technology include high density integration, significant reduction of electrical interconnect length for solving signal delay and other problems occurring in the 2D system-on-chip (SOC) technology, and capability to use TSV technology to integrate chips of various functions (e.g., radio frequency, memory, logics, MEMS, etc.) to fabricate a multifunctional package chip. Hence, the 3D stacking technology based on the TSV interconnect structure becomes a popular chip package technology.
Currently, the fabrication method of the TSV interconnect structure includes providing a semiconductor substrate; depositing a mask layer on the semiconductor substrate, the mask layer having openings corresponding to subsequently formed through vias; etching the semiconductor substrate along the openings to create TSVs inside the semiconductor substrate; forming a copper layer by an electroplating process on the surface of the mask layer as well as the sidewall and the bottom surface of the through vias to fill the through vias; planarizing the copper layer by a chemical mechanical polishing process; removing extra copper layer deposited outside the through vias and the openings; and forming an interconnect structure inside the silicon through vias (TSVs).
However, when thinning the copper layer by the chemical mechanical polishing, copper residues often remain on the mask layer. This affects stability of the formed copper interconnect structure.